档案
日志
相册
视频
分享
2008-07-16 | 【原创】发现vdsp4.5系统服务主频设置的一个BUG（含ADI技术支持回信）
使用ADI系统服务设置BF561主频的时候竟然发现无法设置到600M/100M，跟入查看，发现竟然很有可能是一个BUG，发信一问，果然,是VDSP4.5的一个BUG,原文如下：
| PR52525 - PLL config BUG of VDSP4.5 ? | |
| 发件人： | processor.tools.support (processor.tools.support@analog.com) |
| 发送时间： | 2008年7月8日 21:59:26 |
| 收件人： | |
Regards,
Processor Tools Support
**********************************************************************
Processor Tools Support
Development Tools Product Line
Analog Devices, Inc.
e-mail:processor.tools.support@analog.com
**********************************************************************
CROSSCORE, Analog Devices Development Tools
Sent: 05 July 2008 13:52
To: processor.tools.support@analog.com
Subject: PLL config BUG of VDSP4.5 ?
I just use the vdsp4.5 SYSTEM SEVICE functions to set the PLL of BF561 as below:
{
ADI_PWR_RESULT PWRResult;
ADI_PWR_RESULT Result;
u32 fcclk,fsclk,fvco;
ADI_PWR_COMMAND_PAIR ezkit_power[] = {
{ ADI_PWR_CMD_SET_PROC_VARIANT, (void*)ADI_PWR_PROC_BF561SKBCZ600X }, // Processor variant
{ ADI_PWR_CMD_SET_PACKAGE, (void*)ADI_PWR_PACKAGE_MBGA }, // Packaging type of processor
{ ADI_PWR_CMD_SET_VDDEXT, (void*)ADI_PWR_VDDEXT_330 }, // External voltage supply (3.3V)
{ ADI_PWR_CMD_SET_CLKIN, (void*)33 /* MHz */ }, // 30Mhz oscillator connected to CLKIN
{ ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED,(void*)0 }, // Enable Dual Core Synchronizatio! n
{ ADI_PWR_CMD_END, (void*)0} // No more commands
};
PWRResult = adi_pwr_Init( ezkit_power );
adi_pwr_SetFreq(600000000, 100000000, ADI_PWR_DF_OFF);
}
It`s simple, but can`t work successfully, the PLL_CTL is still 0x1A00,and the PLL_DIV is 0x0005.
the cclk is 429M and sslk is 85M.
I traced the routine with step debug mode, and I find it may be a bug of VDSP ,look at this:
============================== In file adi_pwr.h =========================
#define ADI_PWR_VLEV_085 6
#define ADI_PWR_VLEV_090 7
#define ADI_PWR_VLEV_095 8
#define ADI_PWR_VLEV_100 9
#define ADI_PWR_VLEV_105 10
#define ADI_PWR_VLEV_110 11
#define ADI_PWR_VLEV_115 12
#define ADI_PWR_VLEV_120 13
#define ADI_PWR_VLEV_125 14
#define ADI_PWR_VLEV_130 15
#define ADI_PWR_VLEV_135 16
#define ADI_PWR_VLEV_140 17
----- ADI_PWR_VLEV_MIN :
#define ADI_PWR_VLEV_MIN ADI_PWR_VLEV_085 ====>6
----- ADI_PWR_VLEV_MAX :
#define ADI_PWR_VLEV_MAX ADI_PWR_VLEV_130 ====>15
----- ADI_PWR_NUM_VLEVS :
#define ADI_PWR_NUM_VLEVS ADI_PWR_VLEV_MAX-ADI_PWR_VLEV_MIN+1 ===> 10
=============================== In file adi_pwr.c ===========================
------ fvco:
fvco = adi_pwr_cclk_vlev[ADI_PWR_CCLK_VIDX(adi_pwr_active_config.MaxCoreVoltage)];
------ adi_pwr_active_config.MaxCoreVoltage:
ADI_PWR_VLEV_130 ===>15
------ ADI_PWR_CCLK_VIDX(adi_pwr_active_config.MaxCoreVoltage)];
#define ADI_PWR_CCLK_VIDX(V) (V - ADI_PWR_VLEV_MIN) ===> 9
------ adi_pwr_cclk_vlev :
for (i=0, vlev=ADI_PWR_VLEV_MIN ;i<ADI_PWR_NUM_VLEVS; i++, vlev++)
adi_pwr_cclk_vlev[i] = adi_pwr_cclk_vlev_datasheet[i][adi_pwr_active_config.proc_type]
*adi_pwr_active_config.MHzFactor;
------ adi_pwr_active_config.proc_type:
== 2 (ADI_PWR_PROC_BF561SKBCZ600X)
------ adi_pwr_cclk_vlev_datasheet :
static u32 adi_pwr_cclk_vlev_datasheet [ADI_PWR_TOT_VLEVS][4] = {
/* BF561SKBC750X BF561SKBCZ500X BF561SKBCZ600X BF561SBB600 */
/* ADI_PWR_VLEV_070 */ { CCLK_TBD, 250, 250, 250 },
/* ADI_PWR_VLEV_075 */ { CCLK_TBD, 250, 250, 250 },
/* ADI_PWR_VLEV_080 */ { CCLK_TBD, 250, 250, 250 },
/* ADI_PWR_VLEV_085 */ { CCLK_TBD, 250, 250, 250 },
/* ADI_PWR_VLEV_090 */ { ! ;CCLK_TBD, 313, 313, 313 },
/* ADI_PWR_VLEV_095 */ { CCLK_TBD, 370, 370, 370 },
/* ADI_PWR_VLEV_100 */ { CCLK_TBD, 370, 370, 370 },
/* ADI_PWR_VLEV_105 */ { CCLK_TBD, 444, 444, 444 },
/* ADI_PWR_VLEV_110 */ { CCLK_TBD, 444, 444, 444 },
/* ADI_PWR_VLEV_115 */ { CCLK_TBD, 444, 444, 444&! nbsp; },
/* ADI_PWR_VLEV_120 */ { 600, &n bsp; 500, 602, 500 },
/* ADI_PWR_VLEV_125 */ { 600, 500, 602, 500 },
/* ADI_PWR_VLEV_130 */ { 600, 500, 602, 602 },
/* ADI_PWR_VLEV_135 */ { 600, 500, 602, 602 },
/* ADI_PWR_VLEV_140 */ { 756, 500, 602, 602 }
};
==================================
So,adi_pwr_cclk_vlev[] just have 10 elements, is {250,250,250,250,313,370,444,444,444} ,and the max freq of fvco is 444, but as the table above , ADI_PWR_VLEV_130 -- 602M is the No.11 !
Is that a bug ?how to set the freq to 600M/100M of BF561?
Thanks.
Roxy
分享
评论
想第一时间抢沙发么？